for Digital Circuit Synthesis and Layout
- Exercise #3 is posted (16 December)
- Exercise #2 is posted (22 November)
- A3 is posted (2 November)
- Exercise #1 is posted (1 November)
- A2 posted (11 October)
is extended and is due on class on October 11. Also for A1, for
the output pin equivalence, if there are unused output pins on a logic
block, your may use them. Meaning, your router may use two output
pins for a multi-fanout net, if you find it helps routability. Be
sure, however, you do not have two signals routed on the SAME output
pin (i.e. no signal shorts on output pins!). (1 October)
- Assignment #1 is posted (19 Sept)
- Info about the course paper added.
- The 2013 session of ECE1387 will include an emphasis on high-level synthesis (from C to circuits).
- Course webpage established (28 August)
EA 314 (Engineering
Instructor's Office hours:
Email or phone for an appointment (or drop by my office)
Fridays from 5-7 PM, commencing on September 13, 2012
BA4164 (Bahen Building)
The course covers the approaches and algorithms for
automatic circuit synthesis. Topics covered will include: technology mapping,
partitioning, placement, routing, timing analysis, and high-level
synthesis. The course will include experience with existing CAD tools
and building new tools in C/C++. We will pay special attention to
synthesis issues as applied to Field-Programmable Gate Arrays (FPGAs).
Who should take
The course will interest (at least) three types of
1) Students whose research falls in the area of computer-aided design
for FPGAs or ASICs, or whose research pertains to the architecture of
2) Digital IC design engineers: it is important to know how the tools
you use work!
3) Anyone interested in seeing some real/practical applications of
combinatorial optimization algorithms.
and Lecture Schedule
Another Graphics Package -- more "modern"
(Courtesy of Sandeep Chatterjee, email@example.com)
Assignment #1: routing with pin equivalence (PDF) (circuits)
Assignment #2: analytical placement, net models, power (PDF) (circuits) (solver quick start (PDF) -- no need to compile solver with BLAS)
Assignment #3: B&B partitioning (PDF) (circuits)
ExercisesExercise #1: simulated annealing placement and negotiated congestion routing (PDF) (circuits + arch file) Paper about the VTR project (PDF)
Exercise #2: multi-level partitioning with hMetis (PDF) linux binary (circuits + manual)
The linux binary is tested to work on both EECG and ECF machines.
Exercise #3: LegUp high-level synthesis. Visit this website and
follow the instructions to use LegUp 3.0 on a virtual machine (called
My apologies for the large file size of the VM image, however, it is
MUCH easier to install and use LegUp this way, versus compiling it
yourself (as it needs several libraries, Altera Quartus, ModelSim,
etc.) Note that the main LegUp webpage is: http://www.legup.org
The exercise is based on a tutorial we delivered at the 2013 ACM Int'l Symposium on FPGAs earlier this year: (PDF) (divide.tar.gz)